One of the most fascinating topic I came across in the world of computer architecture is Branch Prediction. We use branch prediction for conditional operations. Before understanding branch prediction let us first understand conditional operations or branch instructions.
Branch instructions in simple words are if-else statements.
One of the most critical challenges processors face is deciding what to do when they encounter a branch instruction(aka conditional operation) — a decision point in the code, such as an if-else statement or a loop.
Branch instructions introduce uncertainty into the instruction pipeline. For instance
if (x > 0)
this_branch();
else
not_that_branch();The processor must decide whether to execute the instructions for this_branch or not_that_branch. In a sequential world, it would wait until the condition is evaluated, but that would stall the pipeline, wasting precious cycles.
Impact on Pipelining
In pipelined processors, multiple instructions are executed simultaneously at different stages. A branch instruction disrupts this harmony:
The pipeline stalls while the condition is resolved.
Instructions already fetched may be incorrect and need to be discarded, wasting time.
Branch prediction is a technique used in CPU (Central Processing Unit) design that attempts to guess the outcome of a conditional operation and prepare for the most likely result. If the prediction is correct, the pipeline flows smoothly. If it’s wrong, the CPU discards the speculative work and resumes with the correct path, introducing a slight delay but still improving overall performance.
Next fetch address after a control flow instrcution is not determined till N cycles in a pipelined processer. Where N cycle is the minimum branch latency.
If we are fetching W instructions per cycle. A misprediction will lead NxW wasted instruction cycles.
Types of Branch Prediction
1. Static Branch Prediction
Fixed Predictions: The processor always predicts the same outcome for a branch. Such as it may predict every branch as “not taken” or “Taken”.
Always Not Taken: Simplest to Implement. It has a low accuracy of around 30%.
Always Taken: There is directional predicition it has a better accuracy of around 70%.Based on Heuristics: Some CPUs assume backward branches (e.g., loops) are likely to be taken, while forward branches are not. It is called BTFN i.e Backward Taken forward not Taken.
2. Dynamic Branch Prediction
Dynamic prediction adapts based on the program’s behavior during runtime. It uses history and patterns to make more accurate guesses.It can adapt to dynamic changes.
Hystersis: Can be considerd as inertia that makes sure that system does not change state quickly.
One-Bit Predictor:
Tracks whether a branch was taken or not during its last execution.Two-Bit Predictor:
Introduces more stability by requiring two mispredictions before changing the prediction. The extra bit provides hystersis.
Global History Predictor:
Tracks the behavior of multiple branches, using patterns in program flow to predict outcomes.
Here binary classifiers are used as Perceptrons. A perceptron maps an input vector X to 0 or 1. Perecptron learns linear function of how vector affects each output. It is just like a single layer neural network.
Tournament Predictor:
Combines multiple prediction strategies and selects the best one dynamically.
Challenges in Branch Prediction
Despite its advantages, branch prediction is not without its challenges:
1. Mispredictions:
When a branch prediction is wrong, the pipeline must discard speculative work and reload the correct instructions, introducing a performance penalty.
2. Complex Patterns:
Branch prediction struggles with irregular or data-dependent branching patterns, such as those found in cryptographic algorithms.
3. Energy Overhead:
Sophisticated branch prediction mechanisms consume additional power and silicon area, complicating energy-efficient designs.
4. Security Risks:
Speculative execution, enabled by branch prediction, has been exploited in vulnerabilities like Spectre and Meltdown. These attacks highlight the need for balancing performance with security.
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